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HIP 3100 - SPI flash memory ctrl w/ AHB-ip-18678
￥10,000.00
| 供应商 | HDL Design House |
|---|---|
| 型号 | SPI flash memory ctrl w/ AHB - HIP 3100 |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | SPI flash memory controller with AHB slave interface Decodes and executes SPI flash memory instructions issued by AHB master Provides accurate control signals timing on SPI flash memory interface Allows efficient data transfers (read/write) between AHB master and SPI flash memories Set of configuration registers to control efficient data transfer between AHB master and SPI flash memories and facilitate software control of SPI controller Off-loads AHB master from executing data transfer and controlling the SPI flash memories Provides the information about the status and outcome of data transfer to AHB master by interrupt mechanism and status register Supports hierarchical organization of SPI flash memories Data transfers can be executed in parallel at SPI memory cluster level providing additional offload level for AHB master Dual port Tx/Rx FIFO for each flash memory cluster |
| 详情页 | View more |
| 附件名称 | HIP3100_spiPB_new.pdf |
| 附件链接 | View more |
HIP 3100 is high performance SPI(Serial Parallel Interface) flash memory controller IP core. It allows high performance implementation of SPI flash memory subsystem on AHB bus. SPI controller (HIP 3100) off-loads AHB master and software from direct control of data transfers to/from flash memory subsystem, generation of SPI memory control signals, and increases overall memory subsystem performances. Up to 4 parallel and independent data transfers to/from memory subsystem can be executed increasing overall performances by a factor of 4 or more. With broad set of configuration registers, control fields, interrupt signals and Tx/Rx FIFOs the communication between software/AHB master is minimized to lowest possible level off-loading software and AHB master from direct control of flash memory subsystem and data transfer execution. HIP 3100 supports different flash memory vendors: Spansion, ATMEL, Winbond, Numonyx. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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