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High Channel Count DMA IP Core for PCI Express-ip-22717
￥10,000.00
| 供应商 | Smartlogic GmbH |
|---|---|
| 型号 | The High Channel Count DMA IP Core for PCI Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces. |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Available for Xilinx or Intel (Altera) Devices. Intel Stratix 10 Support now available. User transmits / receives only user data without PCIe protocol knowledge AXI standard interfaces for easy integration All AXI Interfaces have adjustable Datawidth and separate clocking Supports up to 64 channels for writing and 16 channels for reading Adjustable Priority Control; Link Speeds Gen1-3, Link Widths x1-x8 Supports Scatter / Gather Memory with adjustable pagesize Memory Size up to 4 GByte per Streaming Channel Performance only limited by PCI-Express Bandwidth Based on Xilinx / Intel integrated PCI-Sig compliant PCIe Block (HIP) |
| 详情页 | View more |
| 附件链接 | View more |
The High Channel Count DMA IP Core for PCIExpress is a powerful PCIe Endpoint with
multiple industry standard AXI Interfaces. This
IP addresses continuous streaming applications
from up to 64 different datasources. Each
channel is able to transmit data into a separate
memory area. Up to 16 AXI Stream Masters
read DMA Data from the Host and present it to
the User Logic. Additional 8 AXI4 Masters are
available to interface full AXI or AXI-Lite
peripherals with the Host.
The Link Stability detector module measures
the signal integrity of the PCI Express Link for
lab or production tests to prevent shipments of
faulty devices (Xilinx only).
This IP Core enables the developer to build
complex PCI Express endpoints with no specific
PCI Express Protocol Know How. The user only
transmits/receives payload data and does not
have to build valid PCI Express packets.
Due to its generic architecture, the Multichannel DMA IP Core for PCI Express fits into many
applications.
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