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| 供应商 | Rambus |
|---|---|
| 型号 | Designed for performance and low latency in AI/ML, HPC, data center and graphics applications. |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Flexible delivery of IP core: works with ASIC/SoC layout requirements Speed bins: 4.8, 5.6, 6.4, 8.4 Gbps 16 channels and 32 pseudo-channels Support for 2, 4, 8, 12 or 16 device DRAM stacks Available as optimized HBM3 memory subsystem comprising Rambus HBM3 PHY and controller DFI style interface for easy integration with memory controller Memory controller or PHY can be ASIC interface master (PHY independent mode) Selectable low-power operating states Programmable output impedance Pin programmable support for lane repair |
| 详情页 | View more |
| 附件链接 | View more |
The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory subsystem PHY supports data rates up to 8.4 Gbps per data pin. The interface features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1075.2 GB/s.The PHY is designed for a 2.5D system with a silicon interposer to route signalsbetween the 3D DRAM stack and PHY. Rambus performs complete signal and powerintegrity analysis on the entire 2.5D system to ensure that all signal, power and thermalrequirements are met. By working closely with customers to meet system requirements,Rambus provides design flexibility for a differentiated and easy-to-integrate solution.The PHY is delivered as a fully characterized hard macro and contains all of thenecessary components for robust operation including: ? IO pads? PLL? Clock distribution? Transmit and receive paths? Control logic? Power distribution? Electrostatic discharge (ESD) protection circuitry
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