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| 供应商 | Rambus |
|---|---|
| 型号 | Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibil |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Speed bins: 0.5 Gbps, 1.0 Gbps, 1.5 Gbps, 1.6 Gbps, 1.8 Gbps, 2.0 Gbps 8 channels and 16 pseudo-channels Support for DRAM 2, 4, or 8, stacks DFI 3.1 style interface for easy integration with memory controller Memory controller or PHY can be ASIC interface master (PHY independent mode) Selectable low-power operating states Programmable output impedance Pin programmable support for lane repair ZQ calibration of output impedance SSO noise reduction |
| 详情页 | View more |
| 附件链接 | View more |
HBM is a high-performance memory that features reduced power consumption and a small form factor.? It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications. The Rambus HBM Gen2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.
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