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供应商 | CAST |
---|---|
型号 | UART with FIFOs, IrDA, and Synchronous CPU Interface Core |
类型 | Soft IP |
到期日 | In Production |
源网址 | View more |
特征 | Capable of running all existing 16450 and 16550a software; Fully Synchronous design. All inputs and outputs are based on the rising edge of clock In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO's to reduce the number of interrupts presented to the CPU; Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data; Independently controlled transmit, receive, line status and data set interrupts Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 x clock; Modem control functions (CTSn, RTSn, DSRn, DTRn, and DCDn) Programmable Auto-CTSn and Auto-RTSn; In Auto-CTSn mode, CTSn controls the transmitter In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn; Serial Port has an optional Infrared Data Association (IrDA) data port; Fully programmable serial interface characteristics: 5, 6, 7, or 8 bit charactersEven, odd, or no-parity bit generation and detection1, 1?, or 2 stop bit generationBaud generation False start-bit detection Complete status register Internal diagnostic capabilities: loop-back controls for communications link fault isolation; Full prioritized interrupt system controls |
详情页 | View more |
附件链接 | View more |
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