GDDR6 PHY for Samsung-ip-18136

¥10,000.00
有货
SKU
ip-18136
Brand :
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供应商 Cadence
型号 Lowest latency and highest data rates for data-intensive applications
类型 Hard IP
到期日 Available on request
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特征 Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell) Memory controller interface uses DFI 5.0-like standard with extensions for GDDR6 Internal and external datapath loop-back modes Per-bit DFE, CTLE, and FFE equalization DFI PHY Independent Mode for initialization and training Adaptive and continuous timing recovery Transmit crosstalk cancelation of immediate neighbors 8:1 memory:controller clock ratio for easy controller timing closure
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The latest, the Cadence Denali PHY IP for GDDR6, is comprised of architectural improvements drawn from previous-generation DDR PHYs and Cadence’s 10G, 16G, and 25G SerDes, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. This application-optimized PHY IP can achieve speeds up to 16Gbps across its full-rated range of process, voltage, and temperature, while extensions up to 20Gbps are possible with modifications. The PHY IP for provides a low bit error rate (BER) that can improve bandwidth utilization and maximum latency. The PHY IP is designed to be compatible with standard PCB materials like FR4 up to 16Gbps. The PHY IP is developed by experienced teams with industryleading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into systems on chip (SoCs), and is verified with the Cadence Denali Controller IP for GDDR6 as part of a complete memory subsystem solution.

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