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| 供应商 | IMEC |
|---|---|
| 型号 | Scalable C-programmable VLIW DSP 28nm processor for wireless standards, eg LTE Cat4, IEEE802.11n/ac and DVB |
| 类型 | Soft IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | Flexible power efficient DSP micro-core processor for wireless based band processing Targets WLAN and LTE (LTE Cat4 instance available in 28nm CMOS), the architecture is WLAN 802.11n and 11ac ready C-programmable with customizable instruction set Templatized model with design time parameters defining the instance, and instructions selectable per functional unit High performance operation with instruction level parallelism (ILP) VLIW design and data level parallellism (DLP) for the vector units The 10-issue slot VLIW design includes 32-bit scalar units and 256-bit vector units C-programmable with commercial compiler and debugger support Ready for implementation in deeply scaled technology, such as 28nm CMOS Minimal program memory footprint with optimized instruction format and instruction compression 16-bit fixed point implementation |
| 详情页 | View more |
| 附件链接 | View more |
Imec offers a whitebox license to its flexible and highly efficient DSP processor (branded BOT) for wireless baseband processing. This processor is C-programmable with customizable instruction set, and comes with a commercial compilation and debug tool chain with support. This 28nm CMOS DSP (a 40 nm version is also available) is developed to meet and exceed the high throughput and low power consumption requirements of the latest wireless standards, such as LTE Cat4 (Cat5 for multi-core DSP), connectivity standards such as WLAN IEEE802.11n and 11ac and others such as DVB. The scalable architecture allows for flexibility at design time as well as at run time, supporting many algorithms, modes and throughput, easy to adapt and extend. Extra and/or customized instructions can be added easily to the core. Compiler, RTL code and SystemC models are automatically regenerated when changes are made to the model or instruction set. This DSP uses a 10-issue slot VLIW design with 32-bit scalar slots and 256-bit vector slots, using a 16-bit fixed point implementation, with parallelism both for instruction and data level.
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