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| 供应商 | Comcores |
|---|---|
| 型号 | Ethernet TSN MAC 40G/100G, a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Designed to IEEE 802.3-2018 specification Supports 802.1 Qbu and 802.3 br with extensions available Ultra low latency and compact implementation, and Full duplex Ethernet interfaces 256-bit low latency Ethernet MAC, and 40G/100G data rates with cut-through supported TSN features can be enabled/disabled independently, and IEEE 1588 and 802.1 AS extension available Deficit Idle Count for maximum data throughput supported In-Band FCS supported, and Supports Link verification, jumbo frames and many other options Independent TX and RX Maximum Transmission Unit (MTU) Optionally comprehensive statistics gathering, with easy integration with standard AXI4-lite or APB interface Designed in SystemVerilog and targeting both ASICs and FPGAs |
| 详情页 | View more |
| 附件链接 | View more |
Comcores TSN MAC 40G/100G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and 802.3br Interspersing Express Traffic. This enables the use of the MAC in high speed time-critical applications.
The MAC-core performs the Link function of the 40G/100G Ethernet Standard and is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum.
The core is fully configurable, interfaces easily to standard 40G/100G PCS due to its CGMII interface, and can optionally include IEEE1588.
The Ethernet MAC Core, on the Client side, implements a 256-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard 256-bit CGMII interface on the PHY side.
The core is fully configurable and interfaces easily to standard 40G/100G PCS due to its CGMII interface. Features like IEEE1588 solution, VLAN, and DMA integration can optionally be included. The Ethernet MAC Core, on the Client side, implements a 128-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard 256-bit CGMII interface on the PHY side.
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