EnSilica's eSi-3200 32-bit CPU core is an extremely small, low-cost, low-power processor ideal for integration into ASIC and/or FPGA designs with on-chip memories. It is the mid-range member in the eSi-RISC family of processor cores targeted specifically for low cost and low power applications that require more computational power or a larger address space than is provided by the 16-bit eSi-1600 and that are able to be implemented using on-chip memory.

The cacheless memory architecture of the eSi-3200 allows for deterministic performance, making it particularly suitable for hard real-time control applications. For applications where high performance is required, the 5-stage pipeline allows extremely high clock frequencies to be achieved. While most instructions effectively execute in a single clock cycle, the deep pipeline allows the C and C++ compiler to schedule independent instructions such that instructions that can take multiple cycles to execute, appear to only take 1 clock cycle. Static branch prediction is employed to minimize the cost of branch instructions.

A number of instructions are reserved to allow the user to utilise user defined logic via a simple interface. This allows for otherwise unobtainable performance to be reached for many software inner loops. User defined registers and condition codes are also supported, allowing the most complicated applications to be accelerated.

Instructions are encoded in either 16 or 32-bits, depending upon the size of the operands and the type of instruction. All of the commonly used instructions can be encoded in 16-bits. This ensures that high code density is achieved, while minimizing memory accesses to help conserve power.

For applications that require do not require 32-bit performance or more than 64kB of data memory, the eSi-1600 16-bit processor can be used. This processor features the same ISA as the eSi-3200, reduced to 16-bits. For 32-bit applications requiring cachable off-chip memory, the eSi-3250 processor can be used. All of the eSi-RISC processors RTL and toolchains share a common code base, resulting in an easy migration path for both software and hardware developers, should the demands of an application change.

The toolchain for the eSi-3200 is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customizable Eclipse IDE (Integrated Development Environment). The debugger can connect to the target CPU either via JTAG or a serial interface. Complete C and C++ libraries are supplied. A port of the Micrium uC/OS-II RTOS is also available. The toolchain is available for both Windows and Linux hosts and is available to use at no cost.