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| 供应商 | Eureka |
|---|---|
| 型号 | eMMC 4.5 Card Controller supports HS200, DDR, boot mode and other advanced MMC features |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Compatible with eMMC 4.5 specification Supports HS200 speed mode and Dual Data Rate (DDR) data transfer Enhanced MMC features including Boot, Sleep Mode, Reliable Write, Multiple Partitions and Security Supports eMMC and Removable Card with option for SD 3.0 device support Simple 32-bit bus master interface to DMA data into user memory space Interrupt-based transfer mode to allow local CPU maximum control Two clock domain implementation allows user bus interface and MMC clock operates at different clock domains Process most commands automatically without needing support from user logic. Supports eMMC 4.5 command set with built-in standard slave register set Choice of user interface bus including AXI, AHB, APB, PLB, Avalon, Wishbone and Avalon bus |
| 详情页 | View more |
| 附件链接 | View more |
The eMMC 4.5 Card Slave Controller IP cores provide the simplest way to design a MultiMedia Card (MMC) device compatible to the latest eMMC 4.5 spec. It serves as a bridge between the eMMC bus and user's memory/logic. It contains many flexible design features such as DMA and interrupt operation modes and AHB, AXI, PLB, Avalon, Wishbone and other standard buses that allows it to be easily integrated to any card design architecture.
The eMMC 4.5 Card Slave Controllers processes all the bus request from the eMMC bus automatically. It contains the standard card register set and state machines so that most requests from the host are handled locally without support from the user logic. This frees the user from the eMMC protocol constraints. Only memory data access to the user side are forwarded to user's application logic as read/write request. The IP core can be configured to operate as a DMA engine to access user logic or as a slave to the local MPU through request interrupt.
The eMMC 4.5 Card Slave Controllers processes all the bus request from the eMMC bus automatically. It contains the standard card register set and state machines so that most requests from the host are handled locally without support from the user logic. This frees the user from the eMMC protocol constraints. Only memory data access to the user side are forwarded to user's application logic as read/write request. The IP core can be configured to operate as a DMA engine to access user logic or as a slave to the local MPU through request interrupt.
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