dwc_sd_emmc_tsmc-ip-22275

¥10,000.00
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SKU
ip-22275
Brand :
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供应商 Synopsys
型号 SD/eMMC in TSMC (28nm, 16nm, 12nm, 7nm)
类型 Hard IP
到期日 Available on request
源网址 View more
特征 Compliant with eMMC5.1 and SD 6.0 Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1 Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS) Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device Ease of integration Fully optimized, compliant and interoperable SD/eMMC solution Flexible configuration to target both 4-bit and 8-bit applications Consistent delay line granularity/resolution across process corners Electrically compliant drivers Future proof design
详情页 View more
附件名称 dwc_sd_emmc_phy.pdf
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To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for embedded mass-storage flash memory (eMMC) and removable flash memory card (SD Card), targeting a range of applications.
The DesignWare? SD/eMMC PHY IP, compliant with the latest JEDEC and SD specifications, is a fully integrated hard macro with high-speed IOs and Delay Locked Loop (DLL)/delay lines. Optimized for power and area, the PHY IP is fully verified and configurable for easy integration into application processors. The PHY IP and DesignWare SD/eMMC Host Controller IP offer a fully verified solution that designers can use to integrate the latest embedded and removable memory functionality into their application processor, while speeding time-to-market.

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