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| 供应商 | Synopsys |
|---|---|
| 型号 | PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Physical Coding Sublayer (PCS) block with PIPE interface Supports PCIe 6.0, encoding, backchannel initialization Supports PCIe Lane Margining at Receiver Spread-spectrum clocking (SSC) PCIe power management features, including L0p substate; power gating and power island The multi-channel PHY macro with single clock and control core for higher density with support for both internal and external reference clock inputs PIPE bifurcation as well as PHY macro aggregation for up to 16-lane configurations Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs Automated Test Equipment (ATE) test vectors for complete at-speed production testing Each PHY channel contains its own 7-, 9-, 11-, 13-, 15-, 23-, and 31-bit pseudo random bit sequencer (PRBS), or a user-defined custom 256-bit pattern for internal and external loopbacks |
| 详情页 | View more |
| 附件名称 | dwc_pcie6_phy.pdf |
| 附件链接 | View more |
The multi-channel DesignWare PHY IP for PCI Express (PCIe) 6.0 meets todays demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip interfaces. The PHY's unique DSP algorithms optimize analog and digital equalization and the patent pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra-low-latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enables server and storage applications.
The DesignWare PHY IP for PCIe 6.0 seamlessly interoperates with DesignWare Controller IP for PCIe 6.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology.
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