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| 供应商 | Synopsys |
|---|---|
| 型号 | NVM FTP Trim in TowerJazz (180nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Zero mask adder, single poly, floating gate, logic-only reprogrammable NVM solution 64-bit to 2-Kbit configurations Up to 10,000 write cycle enduranc Up to 15-year data retention at 150°C Automotive Grade 0 temperature compliance (-40°C to 150°C) Single core supply operation, uses 3 metal layers only Silicon-characterized and qualified to meet industry standards (including industry standard IP9000, AEC-Q100 and JESD47F) |
| 详情页 | View more |
| 附件链接 | View more |
The Synopsys DesignWare? Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a standard CMOS and Bipolar-CMOS-DMOS (BCD) processes. Optimized for area and performance, the IP is designed for trim applications that require post package programming, in-field updates, or calibration at multiple temperatures. The reprogrammable NVM IP enables multiple time programmable (MTP) flexibility in similar overall area to one time programmable (OTP) solutions and requires no additional masks or processing steps.
Delivered as a hard IP block, the DesignWare FTP Trim NVM IP operates from a single core supply and includes all the necessary support and control circuitry, including all high-voltage generation and distribution required for programming.
The NVM IP reduces test costs and time by up to 3x by increasing the programming speed for special test modes and simplifying the IP complexity. For example, the IP includes bulk operations that enable designers to program the entire array in a single faster operation. In addition, designers can select test conditions and test limits that emulate temperature effects, thereby eliminating the need for testing across temperatures.
Delivered as a hard IP block, the DesignWare FTP Trim NVM IP operates from a single core supply and includes all the necessary support and control circuitry, including all high-voltage generation and distribution required for programming.
The NVM IP reduces test costs and time by up to 3x by increasing the programming speed for special test modes and simplifying the IP complexity. For example, the IP includes bulk operations that enable designers to program the entire array in a single faster operation. In addition, designers can select test conditions and test limits that emulate temperature effects, thereby eliminating the need for testing across temperatures.
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