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供应商	T2M
型号	DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	Multiplexed LDPC/BCH decoder: The DVB-S2 FEC block can simultaneously decode 8 independent input streams. LDPC decoder: The LDPC decoder can decode normal and short frames and all DVB-S2 and S2X Broadcast and Interactive profiles, but not VLSNR. BCH Decoder: The BCH decoder is able to correct up to 12bits for Code rates where more than 192 redundancy bits are available Packet Delinter: The packet delineator is used for descrambling, checking the integrity of BBFrame headers, processing the cache and data fields and providing a lock indicator
详情页	View more
附件链接	View more

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详情

The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single output interface. The data coming from the 8 demodulators are multiplexed and decoded by the same engine. After decoding, 8 packet delineators do the demultiplexing and DVB-S2 de-framing before sending data to the output transport stream manager. For a 258-MHz clock we may have a maximum data rate of 258 Mchannel-bit/s (megaLLRs)at the input to the FEC decoder. Advanced power-saving features have been implemented, the LDPC stops once the solution is sufficiently converged and the various blocks of the IC (tuner, demodulator, LDPC, Legacy FEC, and so on) may be completely shut down if not required. The device also supports Wake-on-network PID.

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