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| 供应商 | SmartDV |
|---|---|
| 型号 | SmartDV's DMA Controller with AXI IP |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Supports 1-16 channel DMA Transmit and DMA Receive Engine Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification. Supports access for Ring and Chained Descriptor Structures Configurable Transmit and Receive Engine based on Host Memory Data Width Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian) Supports configurable DMA Transmit and DMA Receive FIFO based on Host Memory Data width Supports hardware DMA Control registers that can be written and read by CPU Round Robin algorithm for arbitration between DMA Transmit and Receive Engine to access SOC Master Bus SOC Master bus can be AXI/AHB/APB/OCP/Tilelink/Wishbone Supports AXI Slave bus |
| 详情页 | View more |
| 附件链接 | View more |
DMA Controller with AXI interface is full featured, easy-to-use, synthesizable design that can be used with AXI based systems as a controller to transfer data directly from system memory to IP core or from IP core to system memory. Through its compatibility, it provides a simple interface to any IP core with the appropriate logic in between.
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