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| 供应商 | Cadence |
|---|---|
| 型号 | LPDDR4/3, DDR4/3/3L, up to 4266Mbps |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Application optimized configurations for fast time to delivery and lower risk Memory controller interface complies with DFI standards up to 5.2 Internal and external datapath loop-back modes Per-bit deskew on read and write datapath Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes I/O pads with impedance calibration logic and data retention capability RX and TX equalization for heavily loaded systems Fine-grain custom delay cell for delay tuning |
| 详情页 | View more |
| 附件链接 | View more |
The latest Denali high-speed DDR PHY IP is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The application-optimized DDR PHY IP can achieve speeds up to 4266Mbps. Low-power features include the addition of VDD low-power idle state in the PHY, and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce the overall area by up to 20%. The DDR PHY IP is developed by experienced teams with industry-leading domain expertise and is extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoC and is verified with the Denali controller IP for DDR as part of a complete memory subsystem solution. The Denali DDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.
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