DDR4 Multi-modal PHY-ip-17794

¥10,000.00
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SKU
ip-17794
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供应商 Rambus
型号 Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performan
类型 Hard IP
到期日 Silicon proven
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特征 PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface Autonomous initialization Support for x72 bit channel Support for multiple DRAM widths (x4, x8, x16, x32) Support for single channel, 1 to 4 ranks Selectable low-power operating states DFI 3.1 compliant for easy integration with memory controller Programmable output impedance and on-die termination ZQ calibration of output impedance and on-die calibration Utilizes standard 8-layer 6020 metal layer stack
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The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications. Our PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.

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