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供应商	T2M
型号	DR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	Supports DDR4/DDR3 SDRAM DDR4 JEDEC standard 1.2v I/O (POD_12 I/O) DDR3 JEDEC standard 1.5v I/O (SSTL_15-compatible) 16 bits width, Single Channel DDR4/DDR3 SDRAM Interface. 16 bits for per channel, could support 2 x8 bits DDR3 Memory Clock up to 600MHz, DFI Clock up to 600MHz. Support DDR3 800/1066/1333/1600/1866/2133Mbps; DDR4 1866/2133/2400Mbps Supports DFI like interface 4-bit pre-fetch architecture DLL Lock for 1200MHz
详情页	View more
附件链接	View more

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详情

The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps and DDR4 DRAM speeds from 1866Mbps to 2400Mbps, and target support x16 DDR3/DDR4 SDRAM components, the design include an analog hard macro (CLK/CMD/ADDR/DQ/DQS) and a synthesizable digital design. It supports software auto training includes read gate, read/write data eye timing, and PHY Vref settings. Supports DDR4/DDR3 SDRAM. Optimized for high performance, low latency, low area, low power, and ease of integration, the DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with controllers for a complete DDR (Double Data Rate) interface solution.

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