DDR3L/ LPDDR4/ DDR4 Memory PHY IP in 28HPCP-ip-22126

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SKU
ip-22126
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供应商 T2M
型号 DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)
类型 Soft IP
到期日 Silicon proven
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特征 Supported DRAM type: DDR3L/DDR4/LPDDR4 Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps Interface: SSTL135/POD12/LVSTL Data path width scales in 32-bit increment Four modules for flexible configuration:CA/DQ_X16/DQ_X8/ZQ Programmable output impedance (DS) Programmable on-die termination (ODT) Core power:0.9V, I/O power (VDDQ):1.5V/1.35V/1.2V, RX power:1.8V ESD: 2KV/HBM, 200V/MM, 500V/CDM Support ZQ calibration
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The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ process technology, complies with the most recent JEDEC requirements, is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.

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