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供应商 | Eureka |
---|---|
型号 | DDR3 /DDR2 SDRAM Controller supports AHB, AXI buses and multi-port access |
类型 | Soft IP |
到期日 | Silicon proven |
源网址 | View more |
特征 | Supports standard DDR3 and DDR2 SDRAM devices Page hit detection to support multiple column access without RAS or precharge Pipeline access allows continuous data bursting and hidden commands even with page misses Multiple banks are kept active at the same time Integrated soft PHY captures and synchronize SDRAM data using programmable delay cells or DLL Supports built-in soft DDR PHY or external hard PHY such as DFI Re-arrange SDRAM data according to bus interface burst ordering Supports write leveling, ZQ calibration, On-Die Termination (ODT) and OCD for SDRAM devices Programmable SDRAM access timing and memory configuration Multiple ports with arbiter, multiple clock domains and ECC options |
详情页 | View more |
附件链接 | View more |
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