DDR3 / DDR2 SDRAM Controller-ip-20984

¥10,000.00
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SKU
ip-20984
Brand :
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供应商 Eureka
型号 DDR3 /DDR2 SDRAM Controller supports AHB, AXI buses and multi-port access
类型 Soft IP
到期日 Silicon proven
源网址 View more
特征 Supports standard DDR3 and DDR2 SDRAM devices Page hit detection to support multiple column access without RAS or precharge Pipeline access allows continuous data bursting and hidden commands even with page misses Multiple banks are kept active at the same time Integrated soft PHY captures and synchronize SDRAM data using programmable delay cells or DLL Supports built-in soft DDR PHY or external hard PHY such as DFI Re-arrange SDRAM data according to bus interface burst ordering Supports write leveling, ZQ calibration, On-Die Termination (ODT) and OCD for SDRAM devices Programmable SDRAM access timing and memory configuration Multiple ports with arbiter, multiple clock domains and ECC options
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The DDR3 / DDR2 SDRAM controller allows the user to realize the full data bandwidth of DDR3 SDRAM without concerning with specific SDRAM timing and command protocols. User simply issues read/write access through standard bus interface such as AHB, AXI, or through generic address/data bus interface. The controller core insulates the user from the complicated access restrictions of the SDRAM and uses the most efficient way to access the SDRAM efficiently. It also handles the double data rate data generation and capturing through its built-in DDR PHY. Command protocol such as precharge, refresh, RAS and CAS cycles are also automatically determined by the controller core.
The Controller core utilizes many advanced design technique to efficiently access SDRAM data to achieve maximum data bandwidth. Pipeline processing and multiple pending commands allows the user to generate multiple requests to the SDRAM while current request is still being processed. This allows the data pipeline to be filled and utilized continuously. Fast page access and smart auto-precharge with multiple open pages allows the controller to issue CAS-only access whenever possible to reduce access time to SDRAM memory. Timing parameter and memory organization are fully programmable through the control registers.
With various optional features, the controller can be configured to meet different design requirements. A built-in arbiter allows multiple user buses to share access of the SDRAM. Sophisticated arbitration scheme such as bandwidth and latency guarantee can be used for optimized performance. User interface and SDRAM can also run at different clock domains to provided system design flexibility.
The controller comes with synthesizable soft PHY so it is highly portable to different technologies. It can also be configured to support external hard PHY.

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