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| 供应商 | Digital Blocks |
|---|---|
| 型号 | Hs-mode I2C Controller (3.4 Mbit/s High Speed), Silicon Proven |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | I2C Master / Slave Controller with Parameterized FIFO 2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s) State Machine Control for off-load from the Processor of the I2C Bus Protocol & Payload Byte Transfers Optional AMBA AXI4, AXI3, AHB, APB Interfaces; Direct Memory Interface Compliant with AMBA 2.0 and I2C 2.1 specifications Multi-Master, Clock Synchronization, Arbitration, SCL held low by Slave, & Repeated Start capabilites 13 sources of internal interrupts with masking control |
| 详情页 | View more |
| 附件名称 | DB-I2C-MS-Hs-Mode-DS-V1_1.pdf |
| 附件链接 | View more |
The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s). The DB-I2C-MS-Hs-Mode Controller IP Core can also interface a set of Registers within an ASIC / ASSP / FPGA device as well as interface Memory (e.g. SDRAM / SRAM / FLASH) to an I2C Bus.
The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices. The DB-I2C-MS-Hs-Mode I2C Controller targets applications requiring minimal or none processor overhead while delivering a feature set enabling high performance.
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