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| 供应商 | Digital Blocks |
|---|---|
| 型号 | DMA AXI4-Stream to and from AXI4 Memory Map |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. - MM2S: AXI4-Memory Map Read Data to AXI4-Stream Write Data - S2MM: AXI4-Stream Read Data to AXI4-Memory Map Write Data |
| 详情页 | View more |
| 附件名称 | DB-DMAC-MC2-CS-MM2S-S2MM-DS-V1_2_0.pdf |
| 附件链接 | View more |
The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-stream Interfaces.
Control is managed by Commands that stream in via dedicated Command AXI4-Stream Interfaces, with resulting output Status on Status Stream, AXI4-Stream Interfaces. An alternate release has control through Descriptor read by the IP from memory.
Digital Blocks offers two version releases of the DB-DMAC-MC2-CS-MM2S-S2MM:
? ;High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities. This is for applications with large latencies and need sufficient outstanding memory request to maintain a targeting bandwidth.
? ;Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost
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