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| 供应商 | CEVA |
|---|---|
| 型号 | World's most powerful baseband processor |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Core: Fully programmable DSP architecture incorporating unique mix of VLIW and SIMD vector capabilities Core: Deep pipeline architecture achieving very high speeds for the most extreme use cases Core: 8-way VLIW provides optimal hardware utilization Core: Dual scalar processors for running true multi-threading on common memory sub-system, with dynamic VCU resource allocation per thread Core: Extremely powerful vector processor supports fixed- and floating-point operations with 256 MACs per cycle and 2048-bit wide memory BW, achieving 1600 GOPS Core: Utilizing new generation dual CEVA-BX cores with optimizing LLVM C compiler for protocol, control, and DSP native C code supports very low overhead RTOS multi-tasking with dynamic branch prediction. 30% more performance and 30% code reduction Core: New and improved ISA for accelerating FFT and symmetric FIR Core: x2 improvement in complex FIR and matrix manipulation vs previous generation System: Core streaming interfaces support ultra-low latency System: AMBA 4 compliant matrix interconnect |
| 详情页 | View more |
| 附件链接 | View more |
The CEVA-XC16 is the world’s strongest and fastest vector DSP, built upon the innovative Gen4 CEVA-XC multithread architecture. It is ideally suited to handle the advanced baseband computing needs of modern 5G RAN architectures.
Being a scalable and flexible SDR platform, the CEVA-XC16 can be customized, configured and scaled to address multiple applications, including massive baseband (BBU) aggregation and processing, DU acceleration, OpenRAN deployments, massive MIMO RRUs, multi gigabit modems and ultra-low latency use cases, as well as enterprise and high-end 802.11ax Wi-Fi access points.
The CEVA-XC16 DSP is based on a unified scalar and vector-processing platform, using two independent scalar cores, sharing the same coherent tightly coupled memory sub-system, to facilitate true simultaneous and symmetric multithreading operation. Combined with an innovative dynamic multithread Vector Compute Unit (VCU) resource allocation scheme, it achieves unparalleled efficiency in VCU usage, handling large multi-user allocations and ultra-short latency. This results in fine resolution of resource allocation in both time and frequency, as is required in modern 5G and Wi-Fi baseband processing applications.
The CEVA-XC16 uses deep pipeline and innovative physical design methods that enables it to achieve unparalleled 1.8GHz clock speeds at 7nm process node, clocking a 256 MAC VCU and 2048-bit wide memory access bandwidth, amounting to the world’s most powerful baseband crunching machine, achieving up to 1600 Giga Operations Per Second (GOPS).
The dual scalar DSP cores are based on the CEVA-BX architecture, enhanced to meet the high speed of 1.8GHz. These provide a 30% improvement in both control code efficiency and code size relative to previous CEVA-XC generations.
The new design concepts boost the performance per area for a typical 5G use case by 50%, which amounts to 35% die area savings for a large cluster of cores, as is typical for many wireless baseband processing infrastructure use cases.
Being a scalable and flexible SDR platform, the CEVA-XC16 can be customized, configured and scaled to address multiple applications, including massive baseband (BBU) aggregation and processing, DU acceleration, OpenRAN deployments, massive MIMO RRUs, multi gigabit modems and ultra-low latency use cases, as well as enterprise and high-end 802.11ax Wi-Fi access points.
The CEVA-XC16 DSP is based on a unified scalar and vector-processing platform, using two independent scalar cores, sharing the same coherent tightly coupled memory sub-system, to facilitate true simultaneous and symmetric multithreading operation. Combined with an innovative dynamic multithread Vector Compute Unit (VCU) resource allocation scheme, it achieves unparalleled efficiency in VCU usage, handling large multi-user allocations and ultra-short latency. This results in fine resolution of resource allocation in both time and frequency, as is required in modern 5G and Wi-Fi baseband processing applications.
The CEVA-XC16 uses deep pipeline and innovative physical design methods that enables it to achieve unparalleled 1.8GHz clock speeds at 7nm process node, clocking a 256 MAC VCU and 2048-bit wide memory access bandwidth, amounting to the world’s most powerful baseband crunching machine, achieving up to 1600 Giga Operations Per Second (GOPS).
The dual scalar DSP cores are based on the CEVA-BX architecture, enhanced to meet the high speed of 1.8GHz. These provide a 30% improvement in both control code efficiency and code size relative to previous CEVA-XC generations.
The new design concepts boost the performance per area for a typical 5G use case by 50%, which amounts to 35% die area savings for a large cluster of cores, as is typical for many wireless baseband processing infrastructure use cases.
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