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供应商 | Global IP Core |
---|---|
型号 | CCSDS AR4JA LDPC Decoder and Encoder - Global IP Core |
类型 | Soft IP |
到期日 | Silicon proven |
源网址 | View more |
特征 | CCSDS AR4JA LDPC Code family is quasi-cyclic Irregular parity check matrix Run time configuration for more than one code rate (i.e., 1/2, 2/3, 3/4) Configurable codeword size that supports 2K, 3K, and 4K information words Minimum sum algorithm Layered decoding architecture Soft decision decoding Configurable iteration number Synthesized on ASIC 40nm and Xilinx FPGA (Virtex-UltraScaleVCU 118) Compatible with "LOW DENSITY PARITY CHECK CODES FOR USE IN NEAR-EARTH AND DEEP SPACE APPLICATIONS, CCSDS 131.1-O-2, September 2007" standard |
详情页 | View more |
附件链接 | View more |
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