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| 供应商 | CAST |
|---|---|
| 型号 | AHB Cache Controller Core |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Adds single or multilevel cache memory to originally cache-less deeply embedded processors, DSPs, or ASIPs. Improves access time and reduces bandwidth to DRAM, Flash or EEPROM memories; enables XIP without typical power or performance penalties. Cache Parameters Four-way set associative cache Least Recently Used (LRU) replacement policy Synthesis-time configurable: number of cache lines number of words per line 32-bit words Invalidates cache contents if a write access occurs Easy Integration & Implementation Works with any processor with a 32-bit AHB bus 32-bit AHB slave interface towards the processor 32-bit AHB master interface towards the memory system Uses four single-ported SRAMs: no special type of RAM is required Scan-ready design Supports clock gating |
| 详情页 | View more |
| 附件链接 | View more |
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the memory subsystem. The cache controller core supports a four-way associative cache memory, and implements a Least Recently Used (LRU) replacement policy. The number of cache lines and the cache line width are configurable at synthesis time. The core only caches read accesses and invalidates the cached data if a write access to a cached memory location occurs. Mapping the cache controller to any technology is straightforward, as the core does not require any special type of SRAM modules, only using standard, single-ported SRAMs. Furthermore, the design is scan-ready as it uses only rising-edge triggered flip-flops and contains no internal tri-states. Integration of the core is trouble-free, as the core uses standard 32-bit AHB interfaces, and supports clock gating. The CACHE-CTRL core has been robustly verified and is silicon-proven.
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