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| 供应商 | Silvaco |
|---|---|
| 型号 | Infineon C166S V1 Core with four-stage pipelined CPU and optional MAC unit |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Four-stage pipelined CPU with multiple register banks and single-cycle context switching Most instructions execute in 2 cycles Optional MAC unit 16 * 16 multiply in 1 cycle with MAC unit or 5 cycles without MAC; 32/16 division in 10 cycles Scalable interrupt controller supporting 12–112 interrupt nodes External Bus Controller that supports the Infineon XBus+ protocol and provides support for the off-chip external bus interface On-Chip Debugging System (OCDS) with debug interface supporting hardware, software, and external breakpoints, and access to internal registers and memory through JTAG port |
| 详情页 | View more |
| 附件链接 | View more |
The Infineon C166S synthesizable processor core is derived from the successful C166 microcontroller family and is fully instruction set compatible to run all your legacy code. It has been designed to meet the high performance requirements of real-time embedded control applications. The architecture of the C166S combines the benefits of both RISC and CISC (Reduced and Complex Instruction Set Computing). This well-balanced approach delivers the memory saving code density and fast context switching of CISC with the easy RISC instruction decode that enables fast clocking.
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