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| 供应商 | Andes Technology |
|---|---|
| 型号 | 64-bit CPU Core with Level-2 Cache Controller |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | AndeStar V5 Instruction Set Architecture (ISA), compliant to RISC-V technology Floating point extensions DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing Andes extensions, architected for performance and functionality enhancements Separately licensable Andes Custom Extension (ACE) for customized acceleration 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs Branch predication to speed up control code Memory Management Unit (MMU), Physical Memory Protection (PMP) and Programmable Physical Memory Attributes (PMA) Level-1 and level-2 cache controllers with 64-byte cache line size MemBoost for heavy memory transactions |
| 详情页 | View more |
| 附件链接 | View more |
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compression instructions, "P" Packed-SIMD/DSP instructions, "N" for user-level interrupts and Memory Management Unit (MMU) for Linux support.
AX27L2 features branch prediction, level-1 instruction and data caches, level-2 unified cache, local memories, ECC error protection, and Andes Custom Extension to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. AX27L2 also includes vectored and preemptive interrupts to serve diversified system events, AXI 128-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.
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