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| 供应商 | Andes Technology |
|---|---|
| 型号 | Compact High-Speed 64-bit CPU for Real-time and Linux Applications |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | AndeStar? V5 Instruction Set Architecture (ISA), compliant to RISC-V technology Floating point extensions Andes extensions, architected for performance and functionality enhancements Separately licensable Andes Custom Extension? (ACE) for customized acceleration 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs 16/32-bit mixable instruction format for compacting code density Branch predication to speed up control code Return Address Stack (RAS) to speed up procedure returns Memory Management Unit (MMU) and Physical Memory Protection (PMP) Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios |
| 详情页 | View more |
| 附件链接 | View more |
AndesCore? AX25 is a compact 64-bit CPU IP core based on AndeStar? V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs to access address space over 4GB. AX25 also supports the RISC-V P-extension (draft) DSP/SIMD ISA contributed by Andes, single- and double-precision floating point instructions, and MMU for Linux based applications. AX25 comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension? (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.
AX25's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap? and WFI mode for low power and power management, and JTAG debug interface for development support.
AX25's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap? and WFI mode for low power and power management, and JTAG debug interface for development support.
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