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| 供应商 | Eureka |
|---|---|
| 型号 | All-in-one system controller designed for embedded CPU such as ARM, MIPS and PowerPC |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Fully integrated single chip design provide complete system level functions for all external data access Replaces multiple discrete cores/devices on the system Flexible design adaptive to different system requirements for ARM, MIPS and PowerPC CPU Interactive user-driven requirement specification through web-based tools Multiple different clock domains for CPU, peripheral bus interface, and memory systems Internal point-to-point inter-module connection enhances system performance Concurrent data transfer between CPU, System memory, DMA, serial port, and PCI bus Supports industrial standard buses and devices including PCI, UART, SDRAM, FLASH, DMA, SD bus, CompactFlash and PCMCIA Cache coherency, address translation, arbitration and other advanced features Optimized for ASIC and FPGA implementations |
| 详情页 | View more |
| 附件链接 | View more |
The system controller core connects the system CPU to system memory, PCI bus, IO ports and external communication links. The system controller serves as the bridge between the CPU and the outside world. Its main function is to coordinate data movement in the system. The system controller contains all the major functional modules required for most System-on-Chip (SOC) application. The entire system controller function can be easily integrated into a single ASIC or FPGA.
The system controller contains SDRAM controller, PCI bridge, DMA function, UART, bus arbiter and system control registers. Internal to the system controller, these modules are connected to each other directly to achieve high performance and concurrent data movement between various source and data destinations. Since each module is implemented as synthesizable HDL code, each function can be re-configured or modified as required. All modules are designed with a common interface. The connectivity between the modules can be modified easily to meet different system requirements. Modules not needed for specific application can be removed from the core to minimize die size and gate count.
Different system controllers are available for different CPU types. Currently the CPU supported are: ARM CPU, MIPS CPU with SysAD bus and EC Interface, PowerPC 603, 604, 740, 750, MPC8260, 860, Hitachi SH2, SH3 and SH4. The CPU bus can be 32-bit or 64-bit wide depending on the CPU type. Burst data transfer is supported by the system controller.
The system controller contains SDRAM controller, PCI bridge, DMA function, UART, bus arbiter and system control registers. Internal to the system controller, these modules are connected to each other directly to achieve high performance and concurrent data movement between various source and data destinations. Since each module is implemented as synthesizable HDL code, each function can be re-configured or modified as required. All modules are designed with a common interface. The connectivity between the modules can be modified easily to meet different system requirements. Modules not needed for specific application can be removed from the core to minimize die size and gate count.
Different system controllers are available for different CPU types. Currently the CPU supported are: ARM CPU, MIPS CPU with SysAD bus and EC Interface, PowerPC 603, 604, 740, 750, MPC8260, 860, Hitachi SH2, SH3 and SH4. The CPU bus can be 32-bit or 64-bit wide depending on the CPU type. Burst data transfer is supported by the system controller.
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