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| 供应商 | Eureka |
|---|---|
| 型号 | AHB-to-PCI Bridge Controller with host bridge and perpherial master/target and DMA support |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Fully supports PCI specification 2.2 and 3.0 protocol and all AMBA AHB bus transfers Downstream access allows AHB bus devices such as CPU to access PCI bus Upstream access allows PCI bus devices to access system resources on AHB bus AHB bus and PCI bus operate at independent clock domains Data buffers for write posting and read data re-ordering Supports AHB and PCI burst transfers to maximize data bandwidth Includes PCI bus master, bus target and configuration initiator to generates PCI configuration accesses Read access to PCI bus handled as delay read to prevent system deadlock Automatic handling of configuration register read/write access Optional features include Address Translation, DMA, PCI bus arbiter, Cardbus, PCMCIA, MiniPCI, Power Management, and Hot Swap |
| 详情页 | View more |
| 附件链接 | View more |
The PCI host bridge is designed for interfacing any AHB bus device with the PCI bus and forward data access between the two buses. The host bridge consists of several functional units: AHB bus slave, AHB bus master, data buffer, clock domain crossing logics, and PCI master/target. With typical CPU bus running at higher clock frequency than the peripheral bus, the AHB-PCI bridge allows the AHB and PCI bus to operate at two different clock domains, completely asynchronous to each other.
Any bus mastering devices on the AHB bus can access the PCI bus through the host bridge. The core has multiple data buffers to achieve high speed data posting, allow re-ordering of AHB read data, support delay read, and prevent bus deadlock. Other PCI devices can allso access the AHB bus through the host bridge. The host bridge can be used by the CPU to initialize the entire PCI system during power-up reset. Both type 0 and type 1 PCI configuration are supported. The CONFIG_ADDR and CONFIG_DATA registers required for the PCI configuration mechanism are con-tained in the host bridge.
The EP454 can be used as a host bridge (between CPU and the PCI bus) and as PCI peripheral device. Optional features can be added to customize the controller for different application requirements. DMA controller can be provided for high speed transfer of data between the AHB and PCI bus. Because the DMA controller is built-in to the IP core, it requires minimum usage of existing data bandwidth. Address translation can be used to translate the address between the two buses, provide individual address mapping tailored to each system. Other features such as Cardbus/PC card support, Power management and Hot swap are available as well.
Any bus mastering devices on the AHB bus can access the PCI bus through the host bridge. The core has multiple data buffers to achieve high speed data posting, allow re-ordering of AHB read data, support delay read, and prevent bus deadlock. Other PCI devices can allso access the AHB bus through the host bridge. The host bridge can be used by the CPU to initialize the entire PCI system during power-up reset. Both type 0 and type 1 PCI configuration are supported. The CONFIG_ADDR and CONFIG_DATA registers required for the PCI configuration mechanism are con-tained in the host bridge.
The EP454 can be used as a host bridge (between CPU and the PCI bus) and as PCI peripheral device. Optional features can be added to customize the controller for different application requirements. DMA controller can be provided for high speed transfer of data between the AHB and PCI bus. Because the DMA controller is built-in to the IP core, it requires minimum usage of existing data bandwidth. Address translation can be used to translate the address between the two buses, provide individual address mapping tailored to each system. Other features such as Cardbus/PC card support, Power management and Hot swap are available as well.
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