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| 供应商 | Certus Semiconductor |
|---|---|
| 型号 | ?65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP pr |
| 类型 | Hard IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | 1.0V-3.3V |3.3V IO operation w two independent IO rails Output enable / disable (HiZ when disabled) Power-down control (low-power HiZ upon VDD disable) Schmitt trigger receiver w 55K? selectable pull-up or pull-down resistor ESD: 2KV HBM, 500V CDM, DDC, CEC and HPD compliant Power sequence independence I2C / SVID Open-Drain I/O: Up to 3.3V external supply support External resistor support of 1K-50K Ohm Fail-safe OTP Programming CellIS 6.6V compliant |
| 详情页 | View more |
| 附件名称 | CertusBrochure_TSMC65nm-Library.V1p4.pdf |
| 附件链接 | View more |
Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a low-power HiZ state during power-down. The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and optional internal 55K ohm pull-up or pull-down resistor. ESD protection for two independent IO supplies and core power is constructed in an aggressive footprint. A specialty output cell with matched throughput timings for pulse-width modulation (PWM) applications, along with 5V OTP programming, I2C & SVID open-drain and 3.3V & 5V analog cells complement the GPIO offering. The library is enriched with filler, corner and domain-break cells in digital and analog domains to allow for flexible pad ring construction.
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