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Supports data rates of 2.5 to 32 Gbps
Available in GLOBALFOUNDRIES 22FDX? process node
Optimized for low-power operation and north/south die-edge placement
AC-coupled RX front end with on-chip capacitors
Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
Duplex lane configurations of x4 and x1
LC-PLLs provide a wide range of operating frequencies
Wide range programmable multipliers for reference clock multiplication
Differential reference clock inputs are selectively sourced from C4 or internal ASIC interface pins
Flexible ASIC clocking
The 32 Gbps Multi-protocol SerDes PHY is designed for high performance at very low power for medium reach applications. The 32G Multi-protocol SerDes (MPS) PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed data center, networking and 5G infrastructure applications. How the 32G PHY works The Rambus 32G MPS PHY is a comprehensive IP solution that is optimized for power and area in long-reach 30dB channels typical of communications, networking and data center applications. With high performance and multi-protocol compatibility, the PHY supports data rates from 2.5 to 32 Gbps in a wide range of industry-standard interconnect protocols including PCIe 4.0, JESD204B/C, CPRI and Ethernet. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation. The 32G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features that maximize flexibility in today’s most challenging system environments. This makes the PHY ideal for high-performance wireline and 5G wireless infrastructure applications. For Ultra-Low Power 32G Designs Rambus also offers an ultra-low power 32G SerDes PHY (formerly AnalogX AXLinkIO MP) for medium-reach channels up to 25dB insertion loss. This PHY solution supports PCIe 5.0 and earlier generations, Ethernet to 25.78125 Gbps, Interlaken, JESD 204B/C, CPRI and more. It offers the industry’s best power, area and latency in its class for next-generation applications with the most demanding PPA requirements. It is available on advanced FinFET process nodes.
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