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| 供应商 | NTLab |
|---|---|
| 型号 | 44/70/90 MSPS 12-bit 1-channel pipeline ADC |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | TSMC 180 nm CMOS High speed pipelined ADC 1-channel Resolution 12 bit Conversion rate 44 €“ 90 MHz Low power dissipation: 59.4 mW at 44 MSPS, 84.6 mW at 70 MSPS Total Harmonic Distortion (THD): -70.6 dB at 44 MSPS and FIN = 1.9 MHz, -70.1 dB at 70 MSPS and FIN = 1.9 MHz Spurious-free dynamic range (SFDR): 72.7 dB at 44 MSPS and FIN = 1.9 MHz, 73 dB at 70 MSPS and FIN = 1.9 MHz Signal-to-noise ratio (SNR): 61.6 dB at 44 MSPS and FIN = 1.9 MHz, 62.4 dB at 70 MSPS and FIN = 1.9 MHz Portable to other technologies (upon request) |
| 详情页 | View more |
| 附件名称 | 180TSMC_ADC_13_Brief.pdf |
| 附件链接 | View more |
The low-power high-speed 12-bit ADC employs high-performance differential pipeline architecture. The ADC consists of a core ADC, output logic, timing generation, reference currents circuits. The ADC requires: 1.7 · 2 V analog supply, 1.7 · 2 V digital supply, differential reference voltages 1.15 V and 0.65 V, common mode voltage 0.85 · 1 V, reference current 9.9 · 10.1 uA and differential input clock. The ADC supports standby mode which allows state with minimum power consumption. There is also the ability to configure the operating modes of the ADC by using digital registers.
The block is designed on TSMC 180 nm CMOS technology.
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