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供应商	Certus Semiconductor
型号	A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program
类型	Hard IP
到期日	In Production
源网址	View more
特征	GPIO 1.2V-1.8V operation (IO & core) Selectable 15pF \|30pF load support options at 50MHz Schmitt trigger receiver w 105K? selectable pull-up or pull-down resistor ESD: 2KV HBM, 500V CDM Analog 1.8V and 5V tolerant options 20-36V High-voltage, low leakage cell Low capacitance / RF OTP Programming Cell 7.5V tolerant supply gating cell Flip-chip using client configurable pads Secondary CDM cells
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附件链接	View more

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详情

The Certus TSMC 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node. It features a 1.2-1.8V GPIO with selectable dual drive strengths and optional internal 105K? pull-up or pull-down resistor. ESD protection cells for IO and core supplies are constructed in an efficient 60um x 80um footprint. The analog suite includes 1.8V and 5V low-cap analog / RF cells, a 7.5V OTP programming cell, and an ultra-low leakage / low capacitance 20-36V HV analog cell using only baseline CMOS processing layers. The library is enriched with filler, corner, domain break, and secondary CDM cells to allow for flexible segment construction.

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