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| 供应商 | NTLab |
|---|---|
| 型号 | Rail to rail LVDS receiver 1 Gbps |
| 类型 | Hard IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | iHP SGB BiCMOS 0.13 um 3.3 V power supply 1 Gbps (DDR MODE) switching rates Conforms to TIA/EIA-644 LVDS standards without hysteresis Rail to rail input range Optimized for pad-limited layout design Temperature range: -40 °C to + 85 °C Portable to other technologies (upon request) |
| 详情页 | View more |
| 附件名称 | 130iHP_LVDS_02.pdf |
| 附件链接 | View more |
LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pin (OUTp) to receive data and the control pins (EN_RX, EN_RES, EN_CM) to configure the state of the receiver. EN_RES enables the on-chip 100 ohm resistor. EN_CM enable input common-mode voltage for mode receiving AC coupled. Pins BP_RX and BPC_RX to gets voltage reference from receiver bias. PAD_INp and PAD_INn are complementary input to connect to the bonding pads. This LVDS receiver does not employ hysteresis, and therefore does not comply with the hysteresis requirement of the TIA and IEEE standards for LVDS differential signaling at the specified rates.
The LVDS receiver is designed on TSMC SGB BiCMOS 0.13 um technology.
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