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| 供应商 | Certus Semiconductor |
|---|---|
| 型号 | A16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog |
| 类型 | Hard IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Multi-voltage 1.8V / 3.3V switchable operation 4 selectable drive strengths (25-235MHz @1.8V, 10pF) Independent power sequencing 50? (±20%) source termination across PVT Schmitt trigger receiver w 55K? selectable pull-up or pull-down resistor 30um/37um cell pitch (flip-chip) 2KV HBM, 500V CDM; 2KV IEC 61000-4-2 capable Fail-safe Open-Drain IO and ANALOG ESD 8-metal or 10-metal stack Flip-chip package support (client configurable pads) |
| 详情页 | View more |
| 附件名称 | CertusBrochure_-TSMC16nm-Library.V2p6.pdf |
| 附件链接 | View more |
A key attribute of the Certus 16nm & 12nm IO libraries is their ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell can be configured as input, output, open-source, or open-drain with an optional internal 50K ohm pull-up or pull-down resistor. Four selectable drive strengths are offered (25-235MHz @1.8V, 10pF) to optimize across SSO currents & power. The output driver exhibits 50? (±20%) termination across PVT to reduce reflections at higher operating frequencies. ESD protection for VDDIO, VREF, and core VDD is constructed in an aggressive footprint. A 5V I2C / SMBUS open-drain (fail-safe) cell, 5V OTP programming gate cell and 1.8V & 3.3V analog cells are also available. This library features protection break cells to allow for separate grounds while maintaining ESD robustness.
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