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供应商 | Cadence |
---|---|
型号 | 112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel |
类型 | Hard IP |
到期日 | Silicon proven |
源网址 | View more |
特征 | TSMC 5nm FinFET CMOS Process Power-optimized for ELR and LR links Integrated BIST capable of producing and checking PRBS 56-112Gbps PAM4 or 1-56Gbps NRZ data rates Compact footprint for high-density designs Fully autonomous startup and adaptation without requiring ASIC intervention Best-in-class DSP supports ELR lossy and reflective channels Small area and low power is ideal for high port-density applications Beach-front optimized floorplan allows north-south and east-west SoC edge placement Comprehensive on-chip diagnostic features make system testing/debugging quick and easy |
详情页 | View more |
附件链接 | View more |
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