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10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC-ip-18209
￥10,000.00
| 供应商 | Cadence |
|---|---|
| 型号 | Low-power, long-reach, multi-protocol PHY for PCIe 4.0 |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, QSGMII,and SGMII Supports PCIe L1 sub-states Supports SRIS and internal SSC generation Multi-protocol support for simultaneous independent links Supports internal and external clock sources with clock active detection Automatic calibration of on-chip termination resistors Flexible lane configuration from 1 to 8 lanes Scan, BIST, and serial/parallel loopback functions |
| 详情页 | View more |
| 附件链接 | View more |
The Cadence? 10Gbps multi-protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area (PPA). The PHY IP is a lower-active and low-leakage power design crafted for mobile, wireless IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express? (PCIe?) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, QSGMII, and SGMII specifications. The PCS complies with the PIPE 4.2 interfaces, and provides support for the dynamic equalization features of different protocols. The PHY IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to Cadence or third-party PIPE-compliant controllers. It provides a cost-effective, versatile, and low-power solution for demanding applications. It offers SoC integrators the advanced capabilities, flexibility, and support that meet the requirements of high-performance designs. The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.
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